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RISC: Reduced Instruction set Computer

A limited and single instruction set.

A large number of general purpose registers and use and compiler technology to optimize register usage.

Simple instruction pipeline.

Hardwired control unit.

Register operands with limited addressing modes.

A single chip processor.

On chip cache and floating point processor.

RISC instructions are well suited to pipelines execution

Relatively few instructions
Fixed length, easily decoded instruction format

RISC, or Reduced Instruction Set Computer. is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures.

Complex Instruction Set Computer
CISC is an acronym for Complex Instruction Set Computer and are chips that are easy to program and which make efficient use of memory. Since the earliest machines were programmed in assembly language and memory was slow and expensive, the CISC philosophy made sense, and was commonly implemented in such large computers as the PDP-11 and the DECsystem 10 and 20 machines.

Most common microprocessor designs such as the Intel 80x86 and Motorola 68K series followed the CISC philosophy.
But recent changes in software and hardware technology have forced a re-examination of CISC and many modern CISC processors are hybrids, implementing many RISC principles. 
CISC was developed to make compiler development simpler. It shifts most of the burden of generating machine instructions to the processor. For example, instead of having to make a compiler write long machine instructions to calculate a square-root, a CISC processor would have a built-in ability to do this.

CISC Attributes

The design constraints that led to the development of CISC (small amounts of slow memory and fact that most early machines were programmed in assembly language) give CISC instructions sets some common characteristics:

A 2-operand format, where instructions have a source and a destination. Register to register, register to memory, and memory to register commands. Multiple addressing modes for memory, including specialized modes for indexing through arrays

Variable length instructions where the length often varies according to the addressing mode

Instructions which require multiple clock cycles to execute.
Most CISC hardware architectures have several characteristics in common: 

Complex instruction-decoding logic, driven by the need for a single instruction to support multiple addressing modes.

A small number of general purpose registers. This is the direct result of having instructions which can operate directly on memory and the limited amount of chip space not dedicated to instruction decoding, execution, and microcode storage. 
Several special purpose registers. Many CTSC designs set aside special registers for the stack pointer, interrupt handling, and so on. This can simplify the hardware design somewhat, at the expense of making the instruction set more complex.  
A 'Condition code" register which is set as a side-effect of most instructions. This register reflects whether the result of the last operation is less than, equal to, or greater than zero and records if certain error conditions occur. 
At the time of their initial development, CISC machines used available technologies to optimize computer performance.

Microprogramniing is as easy as assembly language to implement, and much less expensive than hardwiring a control unit.

The ease of microcoding new instructions allowed designers to make CISC machines upwardly compatible: a new computer could run the same programs as earlier computers because the new computer would contain a superset of the instructions of the earlier computers.
As each instruction became more capable, fewer instructions could be used to implement a given task. This made more efficient use of the relatively slow main memory.  
Because microprogram instruction sets can be written to match the constructs of high-level languages, the compiler does not have to be as complicated.  

 CISC Disadvantages
Designers soon realized that the CISC philosophy
had its own problems, including: 
Earlier generations of a processor family generally were contained as a subset in every new version - so instruction set & chip hardware become more complex with each generation of computers.  
So that as many instructions as possible could be stored in memory with the least possible wasted space, individual instructions could be of almost any length - this means that different instructions will take different amounts of clock time to execute, slowing down the overall performance of the machine.  
Many specialized instructions aren't used frequently enough to justify their existence -approximately 20% of the available instructions are used in a typical program. 
CISC instructions typically set the condition codes as a side effect of the instruction. Not only does setting the condition codes take time, but programmers have to remember to examine the condition code bits before a subsequent instruction changes them.

Emphasis on hardware
Emphasis on software
Includes multi-clock
complex instructions
reduced instruction only
"LOAD" and "STORE“
incorporated in instructions
Register to register:
"LOAD" and "STORE“ are
independent instructions
Small code sizes,
high cycles per second
Low cycles per second,
large code sizes
Transistors used for storing
complex instructions
Spends more transistors
on memory registers


A technique used in advanced microprocessors where the microprocessor begins executing a second instruction before the first has been completed.

-A Pipeline is a series of stages, where some work is done at each stage. The work is not finished until it has passed through all stages.

With pipelining, the computer architecture allows the next instructions to be fetched while the processor is performing arithmetic operations, holding them in a buffer close to the processor until each instruction operation can performed.
How Pipelines Works
The pipeline is divided into segments and each segment can execute it’s operation concurrently with the other segments. Once a segment completes an operations, it passes the result to the next segment in the pipeline and fetches the next operations from the preceding segment.  

The processing of an instruction need not be divided into only two steps. For example, a pipeline processor may process each instruction in four steps, as follows:

Fetch: read the instruction from the memory

Decode: decode the instruction and fetch the source operands.

Execute: perform the operation specified by instruction.

Write: store the result in destination location.
Instructions Fetch
The instruction Fetch (F) stage is responsible for obtaining the requested instruction from memory. The instruction and the program counter (which is incremented to the next instruction) are stored in the IF/ID pipeline register as temporary storage so that may be used in the next stage at the start of the next clock cycle. 
Instruction Decode

The Instruction Decode (D) stage is responsible for decoding the instruction and sending out the various control lines to the other parts of the processor. The instruction is sent to the control unit where it is decoded and the registers are fetched from the register file.

The Execution (E) stage is where any calculations are performed. The main component in this stage is the ALU. The ALU is made up of arithmetic, logic and capabilities.

                     Write Back
The Write Back (W) stage is responsible for writing the result of a calculation, memory access or input into the register file. 

Again, pipelining does not result in individual instructions being executed faster; rather, it is the throughput that increases.

Throughput is measured by the rate at which instruction execution is completed.

Pipeline stall causes degradation in pipeline performance.

We need to identify all hazards that may cause the pipeline to stall and to find ways to minimize their impact.

  More efficient use of processor

  Quicker time of execution of large number of  instructions


  Pipelining involves adding hardware to the chip

  Inability to continuously run the pipeline at full speed because of pipeline hazard which disrupt the smooth execution of the   pipeline.

Pipeline Hazards
Data Hazards – an instruction uses the result of the previous instruction. A hazard occurs exactly when an instruction tries to read a register in its ID stage that an earlier instruction intends to write in its WB stage.

Control Hazards – the location of an instruction depends on previous instruction

Structural Hazards – two instructions need to access the same resource


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