Interrupt Structure in Operating System
The connections between the devices and the interrupt controller use interrupt lines on the bus rather than dedicated wires. (sets interrupt bit)
Interrupt Processing
- Each devise asserts a signal on a bus assigned until attended Interrupt controller.
- Controller detects and distinguish the interrupt signal by the device.
- If no other interrupt pending it immediately process the interrupt. Otherwise process high priority interrupt, and ignores the interrupt.
- Controller puts number on address line telling CPU which device wants attention.
- Table (interrupt vector) points to interrupt service routine.
- Number on address line acts as index into interrupt vector.
- Interrupt vector contains PC which points to start of service routine.
→ Interrupt service routine acknowledge interrupt.
→ Saves information about interrupted program.
→ Where to save information,
- Each devise asserts a signal on a bus assigned until attended Interrupt controller.
- Controller detects and distinguish the interrupt signal by the device.
- If no other interrupt pending it immediately process the interrupt. Otherwise process high priority interrupt, and ignores the interrupt.
- Controller puts number on address line telling CPU which device wants attention.
- Table (interrupt vector) points to interrupt service routine.
- Number on address line acts as index into interrupt vector.
- Interrupt vector contains PC which points to start of service routine.
→ Interrupt service routine acknowledge interrupt.
→ Saves information about interrupted program.
→ Where to save information,
- User process stack, kernel stack are both possibilities
- Both have problems
- User process, stack pointer might me illegal may cause fatal error or stack pointer at the end of page may cause page fault, interrupt causing interrupt, difficult to handle that where to save state?
- Save to kernel stack, legal pointer, but trap to kernel space, change MMU, will invalidate TLB and cache, reloading all these is time consuming.
The precise (ideal) interrupt
- PC (Program Counter) is saved in a known place.
- All instructions before the one pointed to by the PC have fully executed.
- No instruction beyond the one pointed to by the PC has been executed.
- Execution state of the instruction pointed to by the PC is known.
Can we save the PC and PSW?
- Sure, if we don't use pipelined or supersscalar CPU's.But we do use them.
- In both cases, we can't assume that all instructions up to the interrupt point and including interrupted instruction have been executed.
Bunch of instructions are partially completed
→ Superscalar
instruction are decomposed and can execute out of order.
Precise and Imprecise Interrupts
b) An imprecise interrupt.
How to process an imprecise interrupt
- With great difficulty
- Either Need complicated hardware logic to re-start after interrupt (Pentium)
- Or have complicated processing in the OS
No comments