Single and Three Bus Architecture

• Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded into the IR (fetch phase).

   IR ← [[PC]]

•  Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase)

  PC ← [PC] + 4

• Carry out the actions specified by the instruction in the IR (execution phase).

                                Figure  : Single-bus organization of the datapath inside a processor.

                                            Figure  : Input and output gating for the registers

Execution of Complete Instruction

                        Ex.     Add (R3), R1

1.Fetch the instruction

2.Fetch the first operand (the contents of the memory location pointed to by R3)

3.Perform the addition

4.Load the result into R1

          Figure: Control Sequence for execution of the instruction Add (R3), R1. 

Execution of Branch Instructions 

•  A branch instruction replaces the contents of PC with the branch target address, which is usually obtained by adding an offset X given in the branch instruction.

•  The offset X is usually the difference between the branch target address and the address immediately following the branch instruction.

             Figure : Control sequence for an unconditional branch instruction

 

 Three-bus organization :-

 

          Figure : Three-bus organization of datapath Multiple-Bus Organization

•Add R4, R5, R6

 

                                      Figure : Control sequence for the instruction.  Add R4,R5,R6,

                                                         for the three-bus organization