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In shift register each CLK PULSE shifts the content of register by one-bit to the RIGHT or LEFT.
The "serial input"determines what goes into the left most flip-f;op during the shift.

Serial - In Serial-Out  (SISO)

4-bit Right - shift SISO Register

- In right shift SISO register , LSB data is applied at the MSB ( D-FF).
- In 'n' bit register , to enter 'n' bit data, it requires 'n' clock pulses in serial form.
- If 'n' bit data is to be stored in SISO register then output to take serially for ( n-1) clock pulese are   required.
- SISO register is used to provide 'n' clock pulse delay to the input data.
- If 'T' is the period of clock pulse, then delay provided by SISO is nT.

4-bit Left-shift SISO Register

- In this above SISO register MSB data is applied to the LSB FF( D-FF).
- To enter the  'n' bit data in serial form we require 'n' clock pulses.
- To exit or getting output of 'n' data as serially we require (n-1) clock pulse.

Serial - In Parallel - Out  (SIPO)

- For n-bit serial input data to be stored the number of CLK pulsesb required = n.
- For n-bit- parallel output data to be stored the number of CLK pulses required = 0 (there is no need of CLK pulses).

Parallel-In Serial-Out  (PISO) 

- It stores parallel data. To store n bit number of CLK pulses required = 1 CLK pulses.
- To give serial out data number of CLK pulse required = ( n-1).

Parallel - In Parallel - Out  (PIPO)

- For parallel in data the number of CLK pulses required = 1 CLK pulse.
- For parallel out data the number of CLK pulses required = 0 CLK pulse.
- Time delay : A SISO SRs may be used to introduce time delay " Ᵹ t " in digital signals.

                                        Ᵹt = N * T = N  * 1/Fc

                                       N = Number of FFs
                                       T = Time period of CLK pulse
                                       Fc = CLK frquency'
- The amount of delay can be controlled by the "Fc" or number of FFs in the SR.  

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