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Microprogrammed Control

•Control signals are generated by a program similar to machine language programs.

•The previous organization cannot handle the situation when the control unit is required to check the status of the condition codes or external inputs to choose between alternative courses of action.

•Use conditional branch micro instruction.

Microinstructions Format:-

•A straightforward way to structure microinstructions is to assign one bit position to each control signal.

•However, this is very inefficient.

•The length can be reduced: most signals are not needed simultaneously, and many signals are mutually exclusive.

•All mutually exclusive signals are placed in the same group in binary coding.

An example of a partial format for field-encoded microinstructions.
Vertical organization:-
•Highly encoded schemes.
•Use compact codes to represent only a small number of control functions in each micro-instruction.
•Slow operating speed, more micro-instructions to generate the required control functions.

Horizontal organization:-
•Minimally encoded schemes. 
•Many control signals can be specified in each microinstruction. Higher operating speeds, useful when the machine allows parallel control of resources.

Microprogram sequencing:-
Simple microprogram sequencing:

- Load the starting address into mPC when a new instruction is loaded into IR. 
- Introduce some branching capability within the microprogram through special branch microinstructions, which specify the branch address.

Disadvantages of the simple approach:

•Large total number of microinstructions and large control store.
•Most machines have several addressing modes, and many
combinations of instructions and addressing modes.  •Separate microroutine for each of these combinations produces a lot of duplication of common parts.
•Share as much common code as possible.
•Sharing common code requires many branch instructions to transfer control among various parts.
•Execution time is longer because it takes more time to carry out the required branches.
Microinstructions with the next-address field:-
•Several branch microinstructions are required to enable sharing of common code.
•The branch microinstructions do not perform any useful operation related to data.
•They are required to determine the address of the next microinstruction.
•They slow down the execution of the instruction.
•Ideally we need to assign consecutive addresses to all microinstructions that are generally executed one after the other.
•Recall that the next microinstruction is determined by incrementing the microprogram counter.
•But due to the goal of sharing as much common code as possible, this is not always possible.
•This leads to a significant increase in the branch instructions.
•Powerful alternative is to include an address field as a part of every microinstruction.
•The address field indicates the location of the next microinstruction to be fetched.
•In effect, every microinstruction becomes a branch microinstruction in addition to its other function.

Additional bits are required to specify the address field in every instruction.
Approximately one-sixth of the control store is devoted to specifying the address.

- Separate branch instructions are virtually eliminated.
- Flexible scheme, very few restrictions in assigning addresses to microinstructions.
- Microprogrammed control leads to slower operating speed because of the time it takes to fetch microinstructions from the control store.
- To achieve faster operation, the next microinstruction can be prefetched while the current one is being executed.
- Execution time can be overlapped with the fetch time.
- Prefetching microinstructions presents some difficulties:Status flags and the results of the current microinstruction that is being executed are necessary to determine the address of the next microinstruction.Straightforward prefetching may occasionally fetch a wrong instruction.
Fetch must be repeated.
Disadvantages/difficulties more than balance the increased operation speed.

Microprogrammed control offers the flexibility to add new instructions to the instruction set of a processor. –New microroutines need to be added to implement the new instructions.
Add to the instruction set of a given computer M1 an entirely new set of instructions that is in fact the instruction set of a different computer M2.
–Programs written in the machine language of M2 can be run on M1.
–M1 emulates M2.
Emulation allows transition to new computer systems with minimal disruption.

Bit Slices

- Using m-Bit Slices of k-bits ALU slices to get m.k-bits parallel operations by an ALU.
- Using serial subunits of k-bits to get m.k-bits operations in m-times the time for one sub unit.
Each bit slice uses separate control memory
- Four slices will be needed in parallel if ALU 64-bits operations are to take nearly the same time as 16-bit slice, and four slices will be needed in series if ALU 64-bits operations are to take nearly four times of 16-bit slice
- Slices used in parallel for ALU operations on large word operands
Each bit-slice uses separate control memory
- Technique for constructing a processor from modules, each of which processes one bit field or "slice" of an operand.
- Bit slice processors usually consist of an ALU of 1, 2, 4 or 8 bits and control lines.
- For example, two 4-bit ALUs could be arranged side by side, with control lines between them, to form an 8-bit ALU.
- A sequencer executes a program to provide data and control signals.
- Bit-slice microprocessors are the Legos of microprocessors. In bit-slice microprocessors the MPU is split apart into CU and ALU chips.

Macro Processor:-
- A macro represents a commonly used group of statements in the source programming language.
- The macro processor replaces each macro instruction with the corresponding group of source language statement, this is called expanding macros .
- The functions of a macro processor essentially involve the substitution of one group of characters or lines for another .

Definition & Expansion:-
The MACRO statement identifies the beginning of a macro definition.
The symbol in the label field is the name of the instruction
The entries in the operand field identify the parameter of the macro instruction.
Each parameter begins with the character &.
The MEND assembler directive marks the end of the macro definition.
A macro invocation statement gives the name of the macro instruction being invoked and the arguments to be used in expanding the macro.

Processor Data Structure
The macro definitions themselves are stored in definition table (DEFTAB), which contains the macro prototype and the statements that make up the macro body
The macro names are entered into NAMTAB, which serves as an index to DEFTAB
For each macro instruction defined NAMTAB contains pointers to the beginning and end of the definition in DEFTAB
The third data structure is an argument table (ARGTAB), which is used during the expansion of macro invocations

When a macro invocation statement is recognized, the arguments are stored in ARGTAB according to their position in the argument list.
  - Recognize macro definitions

  - Save the macro definition

  - Recognize macro calls

  - Expand macro calls

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