Instruction Formats (CAO)

       OP-code field - specifies the operation to be performed

       Address field  - designates memory address(es) or a   

                                      processor register(s)

       Mode field -  determines how the address field is to be 

                                interpreted (to  get effective address or 

                                 the operand)

The number of address fields in the instruction format

depends on the internal organization of CPU.

•Three-Address Instructions

  ADD  R1, R2, R3    R3 ← R1 + R2

•Two-Address Instructions

  ADD  R1, R2               R2 ← R1 + R2

•One-Address Instructions

  ADD  M    AC ← AC + M[AR]

•Zero-Address Instructions     

   ADD  TOS ← TOS + (TOS – 1)

 

Example:   Evaluate X = (A+B) * (C+D)

•Three-Address

1.ADD  A, B, R1  ; R1 ← M[A] + M[B]

2.ADD  C, D, R2  ; R2 ← M[C] + M[D]

3.MUL  R1, R2, X  ; M[X] ← R1 * R2

 

 Example:   Evaluate X = (A+B) * (C+D) 

• Two-Address

 

1.MOV  A, R1   ; R1 ← M[A]

2.ADD  B,R1  ;   R1 ← R1 + M[B]

3.MOV  C, R2   ; R2 ← M[C]

4.ADD  D, R2  ;  R2 ← R2 + M[D]

5.MUL  R2, R1  ;R1 ← R1 * R2

6.MOV  R1, X  ;   M[X] ← R1

 

 • One-Address

1.LOAD  A  ;    AC ← M[A]

2.ADD  B     ;    AC ← AC + M[B]

3.STORE  T  ;   M[T] ← AC

4.LOAD  C   ;    AC ← M[C]

5.ADD  D  ;       AC ← AC + M[D]

6.MUL  T  ;       AC ← AC * M[T]

7.STORE  X  ;   M[X] ← AC

 

• Zero-Address

 

1.PUSH  A  ; TOS ← A

2.PUSH  B   ; TOS ← B

3.ADD  ;        TOS ← (A + B)

4.PUSH   C  ; TOS ← C

5.PUSH  D  ; TOS ← D

6.ADD  ;        TOS ← (C + D)

7.MUL  ;      TOS ← (C+D)*(A+B)

8.POP  X      M[X] ← TOS